5 Concluding Remarks

Table 3: V : power-eecient mapping with min-power t decomp , VI : power-eecient mapping with bh minpower t decomp circuit I II gate delay aver. gate delay aver. Table 1: I : area-delay mapping with conventional decomposition , II : area-delay mapping with minpower t decomp The active cell area is increased by an average of 12.4% while the performance is improved by an average of 1.1%. We have presented algorithms for low power technology decomposition and mapping. In particular, we generate networks with minimum total switching activity and feed them to a delay constrainted power eecient technology mapper which hides the highly active nodes inside the mapped gates. Experimental results show that signiicant reduction in power dissipation is achieved with little or no performance degradation. The idea of generating nodes with minimum switching activity can be extended to the technology independent phase of logic synthesis. Shen et al 12] have already addressed some aspects of this problem. However, more work in node simpliication, common sub-expression extraction and node decomposition is still needed. Technology mapping for low power under real delay model is an important open problem which should be addressed. The average power dissipation also depends on the correlation among primary inputs. For nite state machines and instruction decoder, the correlation probabilities depend on the state and input encoding. Further research needs to be done to address these issues.